A tiny firm wants to slash energy consumption by changing the way CPUs are designed - and it is even planning a new high performance server chip
SMRTR summary
NeoLogic has raised $10 million to revolutionize CPU design with its CMOS+ technology, which enables single gates to handle 6-32 inputs compared to conventional 4-input limitations. The innovation reduces power consumption by up to 50% and chip area by 40% without requiring new manufacturing infrastructure, with first processors expected in data centers by 2026 for energy-efficient AI workloads.
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